
GRAPHIC DESIGNER JOBS SAN FRANCISCO VERIFICATION
Lead cross-functional teams to complete all aspects of pre-silicon verification (simulation, emulation, formal) in a timely manner with first-silicon success.

This includes test planning, testbench development, creating tests, running simulations, debugging, and closing coverage.īuild a diverse, high-performing team by fostering an environment of disruption, collaboration, and inclusion.ĭrive a results-oriented culture with a strong focus on quality, velocity, simplicity, and satisfaction.Ĭollaborate with leaders in product management, architecture, and design to define ASICs optimized across features, performance, cost, and time-to-market. You will lead in the pre-silicon verification and post-silicon validation phases of the product development cycle. You will advise on product definition, architecture, and design. Good verbal and written communication skillsĪbility to work with remote and cross functional teamsĪs a Senior Manager for ASIC Design Verification, you will lead a world-class team of engineers to ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. Scripting languages such as (Python perl/tcl) Peripherals and interconnect protocols such as APB, AHB and AXIĮxperience with the following are a definite advantage:ĭigital Signal Processing designs, usage of Matlab and Simulink Must be able to assist in silicon and FPGA debug and bring-upĮxperience with the following are highly desired Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset domain crossing checks Must have an understanding of low power design and validation techniques including UPF/CPF Must have strong Logic Design, RTL coding (Verilog HDL) and debugging skills BS + ~6 years, MS + ~4 years, or PhD + ~1-2 years with relevant experience in electrical engineering and/or computer architectureīS+15 Years of relevant industry experience.Experience with Unix/Linux environments.Analytical thinking and inventive spirit in combination with a solid understanding of risks and risk mitigation.Solid knowledge of industry-standard tools and practices for analog/mixed-signal and high-speed digital designs (e.g., HSPICE simulator, Cadence design environment).Familiarity with advanced, deep submicron semiconductor technologies (experience with FinFET technology a plus).

Good knowledge in high-speed SerDes design (signaling/equalization techniques, analog/mixed-signal circuit design, and signal integrity).Solid knowledge in fundamental analog design techniques.Layout, Logical Design, Physical Design, Firmware, and Design Verification) to ensure successful cross-team engagement and high-quality execution Work closely with various disciplines (e.g.Drive design and layout reviews to ensure quality of deliverables and mitigate overall risk.

Develop initial circuit schematics and work closely with layout designers to drive designs to completion (including physical verification and backend/reliability flows).Deliver detailed specifications & documentation.Design/implement various state-of-the-art, high-speed (32+Gbps) analog/mixed-signal blocks for SerDes PHYs.
